This invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a quad flat non-lead (QFN) semiconductor package and a method for fabricating the same.
Highly integrated semiconductor packages tend to be decreasingly sized and cost-effectively fabricated in compliance for use with low-profile electronic products. For example of a lead frame based semiconductor package, however, relatively long wire loops and occupied space above the lead frame by gold wires for electrically connecting a chip to the lead frame, may undesirably set certain restriction to dimensional reduction for the package.
In favor of profile miniaturization, U.S. Pat. No. 6,198,171 discloses an QFN (quad flat non-lead) semiconductor package. Referring to FIG. 1, this QFN semiconductor package 1 adopts a lead frame 10 having a die pad 11 and a plurality of leads 12 surrounding the die pad 11, wherein by using half-etching or punching technique, each of the leads 12 is formed at its inner end 122 with a protruding portion 123 that is dimensioned smaller in thickness than the rest part of the lead 12. A chip 14 is mounted on the die pad 11 in an upside-down manner that, an active surface 140 of the chip 14 faces downwardly to be in contact with the die pad 11. A plurality of gold wires 180 are formed to electrically connect the active surface 140 of the chip 14 to the protruding portions 123 of the leads 12. And, an encapsulant 19 encapsulates the die pad 11, the chip 14, the gold wires 180 and a cavity formed underneath the protruding portions 123 of the leads 12.
Due to reduced thickness of the protruding portions 123 of the leads 12, the cavity formed underneath the protruding portions 123 allows to receive the gold wires 180 for use in chip-lead frame electrical connection. With the chip 14 being mounted with its active surface 140 facing toward the cavity, only considerably short gold wires 180 are required to achieve satisfactory electrical connection, making electric transmission and performances of the semiconductor package 1 significantly improved. Moreover, since the gold wires 180 are retained under the leads 12, space above the chip 14 can be more efficiently used for accommodating more chips (as shown in FIG. 2), so as to desirably enhance functionality and processing speed of packaged products.
FIG. 2 illustrates a more advanced multi-chip semiconductor package 1. As shown in the drawing, this multi-chip semiconductor package 1 is characterized in the stacking of a larger second chip 15 on a first chip 14, with an active surface 150 of the second chip 15 being partly in contact with the first chip 14. In order to reduce wire bonding complexity and improve electrical quality, a plurality of solder bumps 16 are formed on the active surface 150 of the second chip 15, for electrically connecting the second chip 15 to top surfaces 120 of the protruding portions 123 of the leads 12.
During fabrication of the foregoing multi-chip package 1, the second chip 15 mounted on the first chip 14 is firstly electrically connected to the protruding portions 123 of the leads 12 by means of the solder bumps 16, and then a wire bonding process is performed for the first chip 14. However, as shown in FIG. 3, when a wire bonder 18 moves to wire contacts 124 of the leads 12 and forms gold wires 180, it applies a force to the wire contacts 124, which force would be in turn transferred to the solder bumps 16 implanted opposite to the wire contacts 124, thereby making the solder bumps 16 crack and even damaging electrical connection quality of the second chip 15.
A primary objective of the present invention is to provide a QFN semiconductor package and a fabrication method thereof, in which wire bonding regions are staggered in position with bump attach regions of a lead frame, whereby solder bumps implanted on the bump attach regions can be prevented from being damaged by force-induced cracks.
Another objective of the present invention is to provide a QFN semiconductor package and a fabrication method thereof, in which wire bonding regions are staggered in position with bump attach regions of a lead frame, whereby the wire bonding regions can be prevented from being contaminated by an etching solution used in solder bump implantation, allowing wire bonding quality to be well assured.
In accordance with the above and other objectives, the present invention proposes a QFN semiconductor package, comprising: a lead frame having a plurality of leads, each of the leads being formed at an inner end thereof with a protruding portion that is dimensioned smaller in thickness than rest part of the lead, wherein the protruding portion has at least a first surface and a second surface opposed to the first surface, and at least a first bonding region is defined on the first surface and staggered in position with a second bonding region formed on the second surface; at least a first semiconductor chip having an active surface and a non-active surface opposed to the active surface, wherein the active surface faces downwardly and is connected to the first bonding regions by a plurality of bonding wires, so as to allow the first semiconductor chip to be electrically coupled to the leads; at least a second semiconductor chip having an active surface and a non-active surface opposed to the active surface, and mounted on the first semiconductor chip, wherein the active surface is electrically connected to the second bonding regions by a plurality of solder bumps; and an encapsulant for encapsulating the first and second semiconductor chips, the bonding wires and the solder bumps.
The invention is characterized in the forming of a protruding portion that is dimensioned smaller in thickness and positioned at an inner end of each lead, wherein a wire bonding region and a bump attach region are defined on opposite surfaces of the protruding portion and staggered in position. By such stagger arrangement, during wire bonding, a force applied by a wire bonder to the wire bonding regions of the protruding portions would not adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions are distantly spaced apart from the bump attach regions, and not easily contaminated by an etching solution such as flux or acid-base rinsing solution used in solder bump implantation, thereby making the wire bonding quality well maintained.